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CPU.DUO.M.T5670/1.8G/2MB/800

KC.56701.DTP
590,90 €
Visa price: inkl. Moms exkl. Moms
Webblager:
Obekräftad

Uppskattad leveranstid: Obekräftad
Leveranskostnad: från 3,90 €
Avhämtning från butiken0,00 €
Postens paketautomat3,90 €
Postpaket5,60 €
Till dörren-paket11,10 €
Hempaket11,70 €
Matkahuolto Närpaket6,20 €
Matkahuolto Busspaket4,10 €
Butiker:välj
Obekräftad
Produktspecifikation
Processor
ProcessorT5670
Processor busshastighet800 MHz
Processorlitografi65 nm
ProcessorfamiljIntel® Core™2 Duo
Lådacross
Processorkärnor2
Processor driftlägen64-bit
Komponent förNotebook
Processorns cache2 MB
Processorfrekvens1,8 GHz
Processorns cachetypL2
Vikt & dimension
Processorns förpackningsstorlek35
Strömtillförsel
VID Spänningsområde1,0375 - 1,3 V
Värmeavledningseffekt (TDP)35 W
Miljökrav
T-junction100 ° C
Grafiken
Ombord grafikkortcross
Processor specialfunktioner
Enhanced Intel Speedstep Technologycheckmark
Egenskaper
Execute Disable Bit-säkerhetcheckmark
Idle statercheckmark
Antal behandlingar Die Transistorer291 M
Bearbetning dö storlek143 mm ²
EAN
Garanti3 månader
Source: Icecat.biz
Beskrivning

Intel® 64
Intel® 64 architecture delivers 64-bit computing on server, workstation, desktop and mobile platforms when combined with supporting software. Intel 64 architecture improves performance by allowing systems to address more than 4 GB of both virtual and physical memory.

Idle States
Idle States (C-states) are used to save power when the processor is idle. C0 is the operational state, meaning that the CPU is doing useful work. C1 is the first idle state, C2 the second, and so on, where more power saving actions are taken for numerically higher C-states.

Enhanced Intel SpeedStep® Technology
Enhanced Intel SpeedStep® Technology is an advanced means of enabling high performance while meeting the power-conservation needs of mobile systems. Conventional Intel SpeedStep® Technology switches both voltage and frequency in tandem between high and low levels in response to processor load. Enhanced Intel SpeedStep® Technology builds upon that architecture using design strategies such as Separation between Voltage and Frequency Changes, and Clock Partitioning and Recovery.

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